JIAWEI HU
MAJOR PROJECTS
Through the Years (Present - 2018)
TSMC MACHINE LEARNING ACCELERATOR, 2024 PRESENT
Currently ongoing...
HETERO-3D: MAXIMIZING PERFORMANCE AND POWER DELIVERY BENEFITS OF HETEROGENEOUS 3D ICS, 2023
This work developed a RTL-to-GDS design flow customized for het- erogeneous 3D ICs. We develop innovative design methodologies encompassing the generation of area-unbalanced 3D floorplans and the optimization of power delivery networks and signal routing based on machine learning models.
BINARY NEURAL NETWORK OPTIMIZATION VIA SDP, 2023
Discrete weight neural network are harder to optimize, often due to non-differentiable binarization function. This work tackles this challenge by designing a randomized algorithm based on Semidefinite Programming (SDP). The advantages of this frame- work are that it provides a more theoretically sound relaxation of the discrete models and that it explicitly models correlations between pairs of weights.
BAYESIAN LEARNING VIA STOCHASTIC LANGEVIN DYNAMICS ON DISCRETE WEIGHT NEU- RAL NETWORK, 2022
By incorporating bayesian learning into the optimization process, we are able to capture the distribution of discrete weights and thus produce better estimate in terms of model performance on test data.
RECONFIGURABLE NEURAL HARDWARE, 2019
Introducing flexibility and configurability to neural hardware for resource-constrained embedded system with compressed neural network.
HARDWARE SECURITY WITH AES ENCRYPTION, 2019
Hardware Implementation of Advanced Encryption Standard algorithm with hard- ware optimisation including pipelining, parallelism, and retiming.
IN-ORDERED PIPELINED ARM PROCESSOR, 2018
Implementation of in-order pipelined ARM core at Register-Transfer Level with hazard detection and branch prediction.
INTEL EMBEDDED SYSTEM DESIGN CONTEST, 2018
Representing NUS winning 2nd Prize in Intel ESDC 2018 with a project on indoor navigation with augmented reality.